Would you like to run your GitHub CI jobs on real RISC-V hardware?
Please reach out at [email protected] or @neo5cloud on X to get free alpha access.
Use runs-on: neo5 and we handle allocation and cleanup automatically as jobs increase.
Our current alpha is open to anyone interested. Get free access at [email protected] or @neo5cloud on X.
We would like to contribute fully transparent builds of software packages and container images on GitHub.
If your open-source project could benefit from our RISC-V CI solutions, please reach out at [email protected] or @neo5cloud on X.
We run a small cluster of Orange PI RV2 machines with 8 cores, 8GB RAM and 200GB+ storage.
After reaching out by email or @neo5cloud on X for alpha access we will allow you to register on our private alpha site.
When you register, you get access to our runner pool.
You then create a GitHub PAT with repository read access, select the number min/max runners you need, and set the runs-on label (for example, neo5) for your workflows.
When you use runs-on: neo5 (or your custom label) in your GitHub workflow, we allocate sandboxed machines to your CI job.
After the job finishes, the sandbox is deleted and the machine is returned to the pool.
Not yet. We are planning to offer this in the future, so please reach out if you are interested.
If you absolutely want to test the native build path, build on the runners.
Otherwise, consider cross-compiling first. It is often much faster than a full native RISC-V build.
For containers, native builds are most useful when you need to execute target-architecture binaries during the image build. If you can prebuild artifacts elsewhere and mostly COPY them into the image, cross-building is usually the better default.
Use the runners when you need accurate testing on real RISC-V hardware, hardware feature validation, or performance evaluation on the target architecture.
For non architecture specific testing most x86 and ARM hardware is still faster. So for now we would not recommend moving over generic test suites to RISC-V just yet.